Continued innovations in semiconductor process technologies are enabling higher integration densities and device scaling. As the semiconductor industry moves towards the 7 nm technology node and beyond, planar and non-planar semiconductor FET device structures must be scaled to smaller dimensions to provide increased device width per footprint area. In this regard, nanosheet (or nanowire) FET devices are considered to be a viable option for continued CMOS scaling. In general, a nanosheet FET device comprises a device channel which comprises one or more nanosheet layers in a stacked configuration, wherein each nanosheet layer has a vertical thickness that is substantially less than the width of the nanosheet layer. A common gate structure is formed above and below each nanosheet layer in a stacked configuration, thereby increasing the FET device width (or channel width), and thus the drive current, for a given footprint area.
One challenge in fabricating nanosheet FET devices is the ability to effectively isolate the nanosheet FET devices from an underlying semiconductor substrate. For example, depending on the FET structure, a parasitic transistor channel is formed in the semiconductor substrate below a bottom of the stacked nanosheet structure, thereby resulting in unwanted current leakage and parasitic capacitance. To suppress leakage current due to the parasitic transistor channel, the semiconductor substrate below the parasitic transistor channel can be heavily doped. However, this approach can lead to increased junction leakage between source/drain regions and the heavily doped semiconductor substrate, as well as parasitic capacitance between the gate and the heavily doped semiconductor substrate.